The present invention generally relates to semiconductor devices and more particularly to an improvement of a CMOS device.
A CMOS (complementary MOS) device is a semiconductor device in which a P-channel MOS transistor and an N-channel MOS transistor are provided on a common semiconductor substrate. Because of the high switching speed and low power consumption, a CMOS device is used extensively in various logic integrated circuit devices including a microprocessor.
In a CMOS device, a P-channel MOS transistor and an N-channel MOS transistor generally operate in a surface channel mode in which carriers are transported along a surface of a channel layer. On the other hand, there is proposed a buried channel CMOS device in which a channel is formed underneath a substrate surface.
FIG. 1 shows the construction of a conventional CMOS structure 10 disclosed in the Japanese Patent Publication 4-26790.
Referring to FIG. 1, the CMOS structure 10 is constructed on a p-type Si substrate 11 on which a P-channel MOS transistor 10A and an N-channel MOS transistor 10B are provided, with a field oxide film 11A intervening therebetween.
It should be noted that the P-channel MOS transistor 10A is provided on an N.sup.- -type surface region formed on the Si substrate 11 in correspondence to he region where the P-channel MOS transistor 10A is to be formed by way of a surface doping process and includes a polysilicon gate electrode 12A of the P.sup.+ -type provided on the foregoing N.sup.- -type surface diffusion region 11f with a gate oxide film 13A intervening between the gate electrode 12A and the substrate surface. Further, the N-channel MOS transistor 10B is provided on a P.sup.+ -type surface region 11g formed on the Si substrate 11 in correspondence to the region where the N-channel MOS transistor 10B is to be formed by way of a surface doping process and includes a polysilicon gate electrode 12B of the N.sup.+ -type provided on the Si substrate 11 with a gate oxide film 13B intervening between the gate electrode 12B and the Si substrate 11 similarly to the gate oxide film 13A.
In the Si substrate 11, there are provided diffusion regions 11B and 11C of the P.sup.+ -type at both lateral sides of the gate electrode 12A respectively as the source and drain regions of the P-channel MOS transistor 10A, with the N.sup.- -type surface region 11f extending therebetween as a surface channel region. Similarly, diffusion regions 11D and 11E of the N.sup.+ -type are formed in the Si substrate 11 at both lateral sides of the gate electrode 12B respectively as the source and drain regions of the N-channel MOS transistor 10B, with the P.sup.+ -type surface region 11g extending therebetween as a surface channel region. Further, both side walls of the gate electrode 12A are covered by side wall insulation films 12A.sub.1 and 12A.sub.2 and both side walls of the gate electrode 12B are covered by side wall insulation films 12B.sub.1 and 12B.sub.2.
Further, the P-channel MOS transistor 10A includes LDD (lightly doped-drain) regions 11b and 11c of the P.sup.+ -type respectively as extensions of the diffusion region 11B and the diffusion region 11C. Similarly, the N-channel MOS transistor 10B includes LDD regions 11d and 11e of the N.sup.- -type respectively as extensions of the diffusion regions 11D and 11E.
In addition, the P-channel MOS transistor 10A includes a layer 14A of the P.sup.- type bridging across the diffusion regions 11B and 11C at a level underneath the LDD regions 11b and 11c. Similarly, the N-channel MOS transistor 10B includes a layer 14B of the N.sup.- -type bridging across the diffusion regions 11D and 11E at a level underneath the LDD regions 11d and 11e. In the CMOS device 10 of FIG. 1, both the P-channel MOS transistor 10A and the N-channel MOS transistor 10B operate as a surface-channel MOS transistor.
By providing the layer 14A or 14B in such a surface-channel MOS transistor, the drain current of the MOS transistor 10A or 10B is increased substantially via the current path provided by the layer 14A or 14B. Associated with the formation of the foregoing current path through the layer 14A or 14B, the problem of hot-carrier injection into the gate oxide film, which tends to occur at a drain edge of the channel region 11f or 11g, is reduced substantially. As the layer 14A or 14B extends fully between the source and drain regions 11B and 11C or between the source and drain regions 11D and 11E, the short channel effect through the layer 14A or 14B is minimized.
On the other hand, the CMOS device of FIG. 1 has a drawback in that the polysi11con gate electrode pattern 12A of the P.sup.+ -type for the P-channel MOS transistor 10A and the polysilicon gate electrode pattern 12B of the N.sup.+ -type for the N-channel MOS transistor 10B have to be formed separately. When the polysilicon gate electrodes 12A and 12B have the same conductivity type such as the N-type or P-type, the threshold characteristics of the MOS transistor 10A or 10B may be modified unwontedly. Further, it is necessary to provide the N.sup.- -type surface diffusion region 11f in the Si substrate 11 selectively in correspondence to the region of the P-channel MOS transistor 10A. Similarly, it is necessary to provide the P.sup.- -type surface diffusion region 11g in the Si substrate 11 selectively in correspondence to the region of the N-channel MOS transistor 10B. Thereby, the number of the mask processes needed for forming the CMOS structure 10 is increased and hence the cost of the CMOS device. Further, it is necessary to form the layer 14A of the P.sup.- -type and the layer 14B of the N.sup.- -type separately by an ion implantation process, while such separately conducted ion implantation processes require additional costly mask processes.
Further, the conventional CMOS device 10 of FIG. 1 has a drawback in that the doped layer 14A of the P-channel MOS transistor 10A may induce a leakage current flowing into the interior of the substrate 11. When this occurs, a drain current is caused to flow even when the transistor 10A is turned off.
FIG. 2 shows another conventional CMOS structure 20 including a buried channel disclosed in the Japanese Laid-Open Patent Publication 6-196642.
Referring to FIG. 2, the CMOS structure 20 includes a P-channel MOS transistor 20A and an N-channel MOS transistor 20B provided commonly on an N-type Si substrate 21, wherein the P-channel MOS transistor 20A and the N-channel MOS transistor 20B are isolated from each other by a field oxide film 21A provided on the substrate 21.
In the structure of FIG. 2, the Si substrate 21 is formed with a P-type well 21W in correspondence to a part thereof in which the N-channel MOS transistor 20B is to be formed, and the surface of the P-type well 21W is covered by a gate oxide film 22B of the N-channel MOS transistor 20B. Further, a polysilicon gate electrode 23B of the N.sup.+ -type is provided on the gate oxide film 22B in correspondence to a channel region 21G of the P-type. Similarly, a gate oxide film 22A is provided on the part of the N-type Si substrate 21 where the P-channel MOS transistor 20A is to be formed, and a polysilicon gate electrode 23A of the N.sup.+ -type is provided on the gate oxide film 22A in correspondence to a channel region 21F of the P-type, which is formed by a surface doping process. The gate electrode 23A is laterally covered by a pair of side wall insulation films 23a. Similarly, the gate electrode 23B is laterally covered by a pair of side wall insulation films 23b.
At both lateral sides of the gate electrode 23A, diffusion regions 21B and 21C of the P.sup.+ -type are formed in the substrate 21 as source and drain regions of the P-channel MOS transistor 20A respectively, wherein the diffusion regions 21B and 21C are provided at the outer sides of the side wall insulation films 23a as usual in the art of MOS transistor. Further, an LDD region 21b of the P.sup.- -type is formed in the substrate 21 between the diffusion region 21B and the P-type channel region 21F, and an LDD region 21c also of the P.sup.- -type is formed between the diffusion region 21C and the P-type channel region 21F.
Similarly, diffusion regions 21D and 21E of the N.sup.+ -type are formed in the P-type well 21W at both lateral sides of the gate electrode 23B, and an LDD region 21d of the N.sup.- -type is provided in the well 21W between the diffusion region 21D and the P-type channel region 21G. Further, an LDD region 21e of the N.sup.- -type is provided between the diffusion region 21E and the P-type channel region 21G.
Thereby, it will be noted that the N-channel MOS transistor 20B operates as an ordinary surface-channel MOS transistor, while the P-channel MOS transistor 20A operates as a buried-channel MOS transistor in which the channel is formed in the interior of the channel layer 22A at a level slightly offset from the surface of the substrate 21.
Further, the P-channel MOS transistor 20A is provided with an N-type layer 24A underneath the P-type channel region 21F, wherein the N-type layer 24A restricts the carrier path extending from the source region 21B to the drain region 21C via the LDD region 21b, the channel region 21F and the LDD region 21c, all having the P-type conductivity type, by inducing a depletion region at the P-N interface between the buried channel layer 24A and the channel region 21F. Thereby, the impurity concentration level of the buried channel layer 24A is set so that the P-channel MOS transistor 20A has a desired threshold voltage. The N-type layer 24A also suppresses the short channel effect.
Further, the N-channel MOS transistor 20B includes an N-type layer 24B underneath the source and drain regions 21D and 21E so as to extend continuously between the source and drain regions 21D and 21E. The N-type layer 24B has an impurity concentration level smaller than the impurity concentration level in the source region 21D or the drain region 21E of the N.sup.+ -type and effectively reduces the junction capacitance formed between the substrate 21 and the source region 21D or the drain region 21E.
As the CMOS structure of FIG. 2 uses an N.sup.+ -type polysilicon pattern commonly for the gate electrode 23A and the gate electrode 23B, the gate electrode 23A and the gate electrode 23B can be formed simultaneously. Further, the P-type layer 21F and the P-type layer 21G can be formed simultaneously by a common surface doping process. Further, the N-type layer 24A and the N-type layer 24B are formed simultaneously by a common ion implantation process. Thereby, the CMOS structure 20 of FIG. 2 can be formed easily and efficiently as compared with the structure of FIG. 1.
In the construction of FIG. 2, it is desired to provide the N-type layer 24A at a level or depth as close as possible to the top surface of the substrate 21 in the P-channel MOS transistor 20A in order to suppress the short channel effect and to control the threshold voltage of the P-channel MOS transistor 20A. On the other hand, in the N-channel MOS transistor 20B, it is necessary and desired to provide the N-channel layer 24B at the bottom level of the diffusion regions 21D and 21E for minimizing the junction capacitance at the drain regions 21D and 21E.
Thus, as long as the layer 24A and the layer 24B are to be formed simultaneously by a common process, it is necessary to form the buried N-type layer 24A also at the bottom level of the source and drain regions 21B and 21C, and the desired effect of suppressing the short channel effect or the control of the threshold voltage in the P-channel MOS transistor 20A cannot be achieved. Generally, it is difficult to reduce the depth of the N-type diffusion region below about 100 .mu.m. Further, the N-type layer 24B of the N-channel MOS transistor 20B, provided underneath the source and drain regions 21D and 21E, does not contribute to the suppressing of the short channel effect.